Memory chips such as dynamic random access memories are fabricated in arrays on semiconductor wafers. After fabrication, some of the chips are inoperable. Functional or operational testing is required to determine which of the chips are inoperable. This testing often utilizes wafer test pads to which external testing circuits are connected.
Many faults within semiconductor chips do not reveal themselves immediately after fabrication. For example, excessively thin layers or areas of insulating oxide may initially provide sufficient insulation to prevent current leakage between adjacent conducting layers. However, these thin layers or areas, with time, will gradually break down, resulting in current leakage between adjacent conducting layers of the semiconductor chip. It is only after this dielectric breakdown that conventional electronic operational testing will detect chip defects.
The phenomenon described above is referred to as "time-dependent dielectric breakdown." The physical structure which results in time-dependent dielectric breakdown varies. For instance, this type of chip defect could be caused simply by an insufficient deposition of insulating oxide. More frequently, a defect is caused by a contaminating particle or impurity within the insulating oxide at a critical location between conductors. Such a particle or impurity has the effect of reducing the insulator thickness over a very small but critical area.
Time-dependent dielectric breakdown is a serious problem since it often takes hours, days, or even years for a defect of this type to manifest itself. Accordingly, functional electronic testing, even if repeated numerous times, is often incapable of detecting this type of defect.
Time-dependent dielectric breakdown is aggravated or accelerated by voltage, time, and temperature. Since time is a constant, semiconductor manufactures sometimes raise testing voltages or temperatures in an attempt to accelerate the effects of marginally defective dielectrics. One common testing method, known as "burning in" a semiconductor chip, involves repeated functional testing at elevated temperatures. The most significant disadvantage associated with this type of testing is the lengthy periods which are required, even at elevated temperatures, to induce actual chip failure in marginally defective chips. A forty-eight hour burn-in cycle is typical. At the high production rates of modern semiconductor manufacturers, burn-in procedures are a significant expense.
Another disadvantage of conventional burn-in procedures is that they can typically be performed only after individual chips are separated from their wafers and packaged. Once packaged, a chip's built-in redundancy features cannot be used to salvage defective circuits within the chip. Furthermore, it is preferable to identify unusable and unsalvageable chips prior to packaging to avoid the expense of packaging.
Accordingly, methods have been developed to induce early breakdown of weak dielectric layers prior to chip packaging. One such method is described in U.S. Pat. No. 4,751,679 to Dehganpour. Dehganpour contemplates testing memory cell gate oxides by imposing an elevated voltage on all of a memory array's row lines simultaneously. Such an elevated voltage aggravates gate oxide defects, in some cases causing their breakdown to the point that defects can be detected in subsequent functional testing.
However, Dehganpour is concerned primarily with testing the gate oxide of memory cell transfer devices. The current state of the art does not adequately address the need for accelerating dielectric failures in other areas of semiconductors and semiconductor memories, such as between column lines, row lines, and storage cell plates. These conductive elements typically intersect each other at numerous points across a memory array, being insulated from each other at their intersections by thin dielectric layers. Marginal defects in dielectric layers at the intersections can eventually result in chip failures.
The invention described below provides a simple and efficient method and circuit for accelerating failure of marginally-defective dielectric layers. The circuits and processes allow defects to be detected at the wafer stage of chip fabrication so that built-in redundancies can be utilized to improve wafer yield, and so that unsalvageable chips can be discarded before packaging. The methods described below also reduce the time required for burn-in testing, resulting in greatly increased testing efficiencies.